Marketplace needs have created a demand for increased fast data-storage capability in an ever-decreasing package size. For many applications, this has translated to efforts to increase the number of memory cells in a given chip size (or real estate area) but using fewer elements to implement each of the cells. The tension between attempting to increase the number of memory cells while using a smaller package, has resulted in a variety of efforts and approaches to memory cell design.
One approach for attempting to minimize the space required for each cell uses three MOS transistors including five access/control lines. The access/control lines include a write select line, a read select line, a ground line, a write bit line and read bit line. The three transistors include a write transistor, an amplifying transistor, and a read transistor. The amplifying transistor has a gate connected to the source of the write transistor to define a (chargeable) storage node. This three transistor design is advantageous in that additional capacitance at the storage node is not required, thereby reducing the space and number of features required to implement such a cell. Further, data stored on the storage node can be read out to the read digit line without destroying the charge level at the storage node. This three transistor design is disadvantageous in that its implementation has required excessive space. In large scale integration, this approach has limited applications.
Another approach uses one transistor and one capacitor with multiple access/control lines. Data is stored at a storage node using the capacitor and is destructively read out of the memory cell through the transistor. The single transistor of this type of cell has combined read and write functions, thereby permitting implementation of this type of memory cell in a relatively small area and rendering the same desirable for large scale integration. For many memory applications, this memory cell design is not preferred because the data within the memory cells is destructively read out.
Yet another approach has been implemented using two transistors without an additional discrete capacitor. For access and control, the cell includes a write row line, a read row line, and a column having a write bit line and a read bit line. One of the transistors is used as the write transistor, and the other transistor is used as a read transistor. The read transistor has its gate acting as the storage node and connected to the source of the write transistor. For many applications, this two-transistor memory cell is advantageous in that information at the storage node can be read nondestructively using only two transistors. Layout implementations for this type of memory cell, however, have been inefficient.